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| P4C1256L LOW POWER 32K x 8 STATIC CMOS RAM FEATURES VCC Current (Commercial/Industrial) -- Operating: 70mA/85mA -- CMOS Standby: 100A/100A Access Times --55/70 (Commercial or Industrial) Single 5 Volts 10% Power Supply Easy Memory Expansion Using CE and OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages --28-Pin 600 mil DIP --28-Pin 300 mil CERDIP --28-Pin 300 mil Narrow Body SOP DESCRIPTION The P4C1256L is a 262,144-bit low power CMOS static RAM organized as 32Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V10% tolerance power supply. Access times of 55 ns and 70 ns are available. CMOS is utilized to reduce power consumption to a low level. The P4C1256L device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A14. Reading is accomplished by device selection (CE and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE or OE is HIGH or WE is LOW. Package options for the P4C1256L include 28-pin 600 mil DIP, 28-pin 300 mil CERDIP, and 28-pin 300 mil Narrow Body SOP packages. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION DIP (P6, D5-2), SOP (S11-3) TOP VIEW Document # SRAM121 REV E Revised June 2007 1 P4C1256L RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE Temperature Range (Ambient) Commercial (0C to 70C) Industrial (-40C to 85C) Supply Voltage 4.5V VCC 5.5V 4.5 VCC 5.5V MAXIMUM RATINGS(1) Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device reliability. Symbol VCC VTERM TA STG IOUT ILAT Parameter Supply Voltage with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Ambient Temperature Storage Temperature Output Current into Low Outputs Latch-up Current >200 Min -0.5 -0.5 -55 -65 Max 7.0 VCC + 0.5 125 150 25 Unit V V C C mA mA DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Symbol VOH VOL VIH VIL ILI ILO Parameter Output High Voltage (I/O0 - I/O7) Output Low Voltage (I/O0 - I/O7) Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current VCC Current TTL Standby Current (TTL Input Levels) VCC Current CMOS Standby Current (CMOS Input Levels) GND VIN VCC GND VOUT VCC CE VIH VCC = 5.5V, IOUT = 0 mA CE = VIH VCC = 5.5V, IOUT = 0 mA CE VCC -0.2V Ind'l. Com'l. Ind'l. Com'l. Test Conditions IOH = -1mA, VCC = 4.5V IOL = 2.1mA 2.2 -0.5 -5 -2 -5 -2 (3) Min 2.4 Max Unit V 0.4 VCC + 0.3 0.8 +5 +2 +5 +2 3 V V V A A ISB mA ISB1 100 A Document # SRAM121 REV E Page 2 of 11 P4C1256L CAPACITANCES(4) (VCC = 5.0V, TA = 25C, F = 1.0 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Conditions VIN = 0V VOUT = 0V Max 7 9 Unit pF pF POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol ICC Parameter Dynamic Operating Current Temperature Range Commercial Industrial * -55 70 85 -70 70 85 -55 15 25 ** -70 15 25 Unit mA mA *Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e. CE and WE VIL (max), OE is high. Switching inputs are 0V and 3V. **As above but @ f=1 MHz and VIL/ VIH = 0V/ VCC. AC ELECTRICAL CHARACTERISTICS - READ CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol tRC tAA tAC tOH tLZ tHZ tOE tOLZ tOHZ tPU tPD Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time Chip Disable to Power Down Time 0 55 5 20 0 70 -55 Min 55 55 55 5 5 20 30 5 25 5 5 25 35 Max Min 70 70 70 -70 Max Unit ns ns ns ns ns ns ns ns ns ns ns Document # SRAM121 REV E Page 3 of 11 P4C1256L TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5) OE TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7) CE Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than -3.0V and -100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 5. WE is HIGH for READ cycle. 6. CE is LOW and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE transition LOW. 8. Transition is measured 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9. Read Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM121 REV E Page 4 of 11 P4C1256L AC CHARACTERISTICS - WRITE CYCLE (Over Recommended Operating Temperature & Supply Voltage) -55 Symbol Parameter Min Max tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write 5 55 50 50 0 40 0 25 0 25 5 -70 Min 70 60 60 0 50 0 30 0 30 Max Unit ns ns ns ns ns ns ns ns ns ns TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10,11) WE Notes: 10. CE and WE must be LOW for WRITE cycle. 11. OE is LOW for this WRITE cycle to show tWZ and tOW. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state 13. Write Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM121 REV E Page 5 of 11 P4C1256L CE TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(10) AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level GND to 3.0V 3ns 1.5V TRUTH TABLE Mode Standby Standby DOUT Disabled Read Write CE H X L L L OE WE X X H L X X X H H L I/O Power High Z Standby High Z Standby High Z DOUT High Z Active Active Active 1.5V Output Timing Reference Level Output Load See Figures 1 and 2 Figure 1. Output Load * including scope and test fixture. Figure 2. Thievenin Equivalent Note: Because of the high speed of the P4C1256L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 F high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50 test environment should be terminated into a 50 load with 1.77V (Thevenin Voltage) at the comparator input, and a 589 resistor must be used in series with DOUT to match 639 (Thevenin Resistance). Document # SRAM121 REV E Page 6 of 11 P4C1256L DATA RETENTION CHARACTERISTICS Symbol VDR ICCDR tCDR tR *TA = +25C tRC = Read Cycle Time Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Test Conditons Min 2.0 Typ.* VCC = 2.0V 3.0V Max VCC = 2.0V 3.0V Unit V CE VCC -0.2V, VIN VCC -0.2V or VIN 0.2V 0 tRC 10 15 600 900 A ns ns This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM Document # SRAM121 REV E Page 7 of 11 P4C1256L ORDERING INFORMATION SELECTION GUIDE The P4C1256L is available in the following temperature, speed and package options. Temperature Range Commercial Speed (ns) Package Plastic DIP, 600 mil Ceramic DIP (CERDIP) Plastic SOJ, 300 mil Industrial Plastic DIP, 600 mil Ceramic DIP (CERDIP) Plastic SOJ, 300 mil 55 -55PC -55DC -55SNC -55PI -55DI -55SNI 70 -70PC -70DC -70SNC -70PI -70DI -70SNI Document # SRAM121 REV E Page 8 of 11 P4C1256L Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 D5-2 28 (300 mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.485 0.240 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0 15 CERDIP DUAL IN-LINE PACKAGE Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L P6 28 (600 mil) Min Max 0.090 0.200 0.000 0.070 0.014 0.020 0.015 0.065 0.008 0.012 1.380 1.480 0.485 0.550 0.600 0.625 0.100 BSC 0.600 TYP 0.100 0.200 0 15 PLASTIC DUAL IN-LINE PACKAGE Document # SRAM121 REV E Page 9 of 11 P4C1256L Pkg # # Pins Symbol A A1 B C D e E H h L S11-3 28 (300 Mil) Min Max 0.094 0.110 0.002 0.014 0.014 0.020 0.008 0.012 0.702 0.710 0.050 BSC 0.291 0.300 0.463 0.477 0.010 0.029 0.020 0.042 0 8 SOIC/SOP SMALL OUTLINE IC PACKAGE Document # SRAM121 REV E Page 10 of 11 P4C1256L REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR A B C D ISSUE DATE 1997 Oct-05 Jun-06 Aug-06 Mar-07 SRAM121 P4C1256L LOW POWER 32K x 8 STATIC CMOS RAM ORIG. OF CHANGE DAB JDB JDB JDB JDB DESCRIPTION OF CHANGE New Data Sheet Change logo to Pyramid Added 28-pin ceramic DIP Added Lead Free Designation Corrected Narrow SOP width in Ordering Information and Selection Guide Corrected Narrow SOP package dimensions E Jun-07 JDB Document # SRAM121 REV E Page 11 of 11 |
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